1. Field of the Invention
The present invention generally relates to data-transmission systems using buses, and particularly relates to a data-transmission system employing a high-speed bus provided with termination.
2. Description of the Related Art.
As a processing speed of microprocessors increases, increased speed of data transmission is required between LSI chips employing an increased frequency of transmission signals. A TTL level and a CMOS level, which are input/output signal levels used in the related-art technology, suffer detrimental effects of signal reflections and crosstalk when a signal frequency exceeds about 50 MHz. In such a case, error-free data transmission becomes difficult.
In order to obviate this problem, input/output interfaces such as CTT (center tapped termination) and GTL (gunning transceiver logic) have been created, which use small-amplitude signals which have signal levels smaller than 1 V.
FIG. 1 is an illustrative drawing showing a GTL system. The GTL system of FIG. 1 includes a bus 10 having characteristic impedance Z.sub.0, termination resistances Rt each connecting a respective end of the bus 10 to a termination voltage Vtt, stubs (or branch lines) 11 each having a characteristic impedance Z.sub.1 and stemming from the bus 10, and devices 20 connected at a respective end of each stub 11, such devices including memories, controllers, etc. Here, the termination voltage Vtt is 1.2 V, and the termination resistance Rt is 50 .OMEGA..
An I/O node of the device 20 connected to the stub 11 has connections to an output circuit and an input buffer circuit in the device 20. The output circuit of the device 20 includes a damping circuit 21 and a driver transistor 22. The input buffer circuit of the device 20 includes a current-mirror-type differential amplifier comprising transistors 23 through 27, and includes an inverter 28. The current-mirror-type differential amplifier makes a comparison between a signal voltage applied to the I/O node and a reference voltage Vref, and outputs a low voltage level to the inverter 28 if the signal voltage is higher than the reference voltage Vref. If the signal voltage is lower than the reference voltage Vref, the current-mirror-type differential amplifier supplies a high voltage level to the inverter 28. The inverter 28 inverts a supplied voltage to provide the inverted signal to internal circuits of the device 20.
One of the advantages of the GTL system is that a wired-OR logic function can be implemented via a bus connection since the driver circuit (output circuit) uses a transistor of an open-drain type as shown in FIG. 1. Another advantage is that a logic state on the bus 10 is either high or low, and is fixed to high when all drivers sharing the bus 10 are turned off. On the other hand, tri-state bus systems such as CTT have a logic state which is an intermediate level between high and low when all drivers are turned off. The input buffer circuit connected to the bus 10 thus receives a signal which cannot be determined as either high or low, and goes into an unstable state randomly detecting highs and lows depending on underlying noise. In order to avoid this, CTT systems need a command to prohibit operations of the input buffer circuits when all the drivers are tuned off.
A disadvantage of the GTL system is a generation of ringing waveforms after turning off of the drivers. Such ringing waveforms are created when a distance between the bus 10 and the driver transistor 22 is long (i.e., the stub 11 is long). For example, a signal frequency of 200 MHz and a length of the stub 11 above 2 mm create large ringing waveforms. Such ringing waveforms become apparent especially when there is parasitic inductance in lead frames and bonding wires.
FIG. 2 is an illustrative drawing showing parasitic inductances L.sub.1 and C.sub.1 present in lead frames and bonding wires. In FIG. 2, turning off of a switch S, which models the driver transistor 22, generates a counterelectromotive force because of sudden cutting off of an electric current, resulting in a voltage pulse heading toward the bus 10 via the stub 11. Since an intersection between the stub 11 and the bus 10 has an impedance mismatch, this voltage pulse is reflected at the intersection between the stub 11 and the bus 10, returning to the driver transistor 22 via the stub 11. The turned-off driver transistor 22 forms an open end, so that the voltage pulse is subjected to a 100% reflection to return to the stub 11. There reflections are repeated, thereby creating intense ringing waveforms between the driver transistor 22 and the intersection of the stub 11 with the bus 10.
FIGS. 3A through 3D are charts showing computer-simulated ringing waveforms. FIG. 3A shows a case in which a stub length is zero. FIG. 3B shows a case in which a stub length is 1 cm. FIG. 3C is a case of the stub length being 2 cm, and FIG. 3D is a case in which the stub length is 5 cm.
FIG. 4 is an illustrative drawing showing conditions of the computer simulations. The computer simulations envisage a case where a driver DV writes data into a memory M.sub.1 by using a signal frequency of 100 MHz under conditions that the driver DV and eight memories M.sub.1 through M.sub.8 are connected to a two-way data bus.
In FIGS. 3A through 3D, solid lines show waveforms at a driver end of the driver DV which writes the data into the memory M.sub.1, and dashed lines show waveforms at a receiver end of the memory M.sub.1. As shown in FIGS. 3A through 3D, the longer the stub length, the more intense the ringing waveforms.
In order to suppress the ringing waveforms, the driver transistor 22 can be controlled so as to achieve slow turning off. The damping circuit 21 of FIG. 1 is provided for this purpose, and controls the driver transistor 22 to carry out slow turning off. The use of such a damping circuit 21, however, places a cap on a maximum operation frequency of the device 20, and, thus, is not preferable.
In light of these, a conventional technique for suppressing the ringing waveforms is to make the stub 11 short enough. Sufficient suppression of the ringing waveforms, however, requires the device 20 to be directly connected to the bus 10 by removing the stub 11. If the device 20 is a memory IC, for example, the memory IC thus needs to be directly connected to bus wires on a mother board. In this case, memory ICs cannot be used in a module form. That is, since the memory ICs are directly connected to the bus wires, the memory ICs cannot be attached or detached freely. Expansion of memory ICs through attachment of new memory ICs, for example, thus become impossible.
Further, another problem arises if the memory ICs are directly attached to the bus 10 by removing the stub 11. This problem is that a so-called shrink technology for reducing the size of memory chips cannot be used. Memory-chip manufacturers generally achieve cost cuts by reducing the size of memory chips. A reduction in the size of a memory chip, however, requires an increase in the length of lead frames connecting between a memory chip inside a package and pins provided outside the package, and this increase in the lead-frame length should be achieved without changing wire arrangements on the mother board. The increase in the lead-frame length therefore ends up creating stubs. In other words, the shrink technology cannot be used when memory ICs are directly connected to a bus.
Another disadvantage of the GTL system is that the relatively low termination voltage of 1.2 V temporarily creates a signal level on the bus having an intermediate voltage level between the high level and the low level. This intermediate voltage level is observed at an instance between when a given device produces a low output and when another device is selected to replace the given device to output a low level.
FIGS. 5A through 5D are illustrative drawings for explaining a process in which an intermediate voltage level is created on a bus. At an initial state as shown in FIG. 5A, driver D1 is selected to be in an on-state (low-output state) among drivers D1 and D2 connected to the bus 10. In this state, the bus 10 is kept at a low voltage (0.4 V), and a receiver R detects this low voltage. The driver D1 has a current amount of 32 mA flowing therethrough.
Then, as shown in FIG. 5B, the driver D1 is unselected and turned off, and the driver D2 is selected to be an on-state (low-output state). In this state, the bus 10 is pulled up to the high voltage (1.2 V) in a proximity of the driver D1 by a termination resistance Rt1. This high voltage is detected by the receiver R. In this state, however, information that the driver D1 is turned off has not yet reached the position of the driver D2. Namely, the high voltage pulled up by the termination resistance Rt1 has not yet reached the position of the driver D2. The bus 10 in proximity of the driver D2 thus still remains at a low voltage (0.4 V), with an insufficient current amount (less than 32 mA) flowing through the driver D2. In the proximity of the driver D2, a current provided from a termination resistance Rt2 flows into the driver D2, and, at the same time, flows toward the driver D1 which on appearance remains at the on-state. This situation is equivalent to that in which both the drivers D1 and D2 are on, thereby producing a voltage lower slightly than 0.4 V on the bus 10 in the proximity of the driver D2.
FIG. 5C shows a state slightly after the state of FIG. 5B, where the high voltage pulled up by the termination resistance Rt1 after the turning off of the driver D1 has reached the position of the driver D1. In this state, the off-state of the device D1 is observed at the position of the driver D2, so that the driver D2 is provided with the sufficient current amount (32 mA) and is fully turned on. Also, the voltage on the bus 10 becomes the low voltage (0.4 V) in the proximity of the driver D2. However, the receiver R has not yet received the information that the driver D2 is fully turned on. Namely, this is a state in which the information that the driver D1 is turned off reached the position of the driver D2, and is returning back on the bus 10 toward the receiver R. The state that the receiver R can detect is that the driver D1 is off and the driver D2 is half turned on. The voltage on the bus 10 in the proximity of the driver D1 becomes an intermediate level between the high level and the low level.
FIG. 5D shows a stabilized state in which the driver D1 is off and the driver D2 is on. In this state, the information that the driver D2 is fully turned on reaches across the entire bus 10, so that the voltage on the bus 10 and the voltage which the receiver R detects become the low voltage (0.4 V).
In this manner, the bus 10 shows the intermediate voltage level for a short instance.
FIG. 6 is a chart showing an appearance of the intermediate voltage level in a computer simulation. A waveform shown in FIG. 6 is detected by the receiver R, and has the intermediate voltage levels appearing for an instance between the high level and the low level, as indicated by arrows. As is understood from the above description, the receiver R cannot avoid detecting the high voltage for an instance. The intermediate voltage level following the high voltage, however, further limits the speed of switching operations switching from the driver D1 to the driver D2. Namely, the system's operation should wait for a period T1 shown in the figure, because the period T1 does not have correct signal levels on the bus.
The generation of the intermediate voltage level can be avoided by raising the termination voltage of the bus 10 from 1.2 V to approximately 2.5 V. Use of the 2.5-V termination voltage, for example, results in a high voltage being applied to the drains of the drivers D1 and D2. The driver D2 thus has a sufficient current amount (32 mA) flowing therethrough even at the state shown in FIG. 5B. This means that the driver D2 is fully turned on from the beginning to draw in a sufficient current amount, thereby producing no intermediate voltage level on the bus. In this manner, if the driver transistors operate within such a range that the driver transistors become a constant current source when turned on, the problem of the intermediate voltage level can be avoided.
The use of such a termination voltage as 2.5 V in the GTL system, however, is not preferable because such a high voltage brings about an increase in power consumption of the drivers.
Accordingly, there is a need, in the data-transmission system using open-drain-type drivers and a bus provided with termination resistances, for a technique which suppresses ringing created by turning off of the drivers without shortening a stub length.
Also, there is a need, in the data-transmission system using open-drain-type drivers and a bus provided with termination resistances, for a technique which eliminates an intermediate voltage level appearing during the time of device switching by raising a termination voltage without incurring an increase in power consumption of devices.